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RF3159
QUAD-BAND GSM/EDGE/GSM850/EGSM900 /DCS/PCS/POWER AMPLIFIER MODULE
RoHS Compliant & Pb-Free Product Package Style: Module (6mmx6mm)
HB RFIN 1
18 HB RFOUT
BAND SEL 2
Features
High Gain for use in Systems with Low RF Driver Power Linear EDGE and GSM Operation PowerStar(R) GSM/GPRS Power Control Digital Band Select Enables GSM850, EGSM900 or DCS, PCS Amplifier Lineup Single Supply Voltage; Requires no External Reference Voltage Automatic VBATT Tracking Circuit avoids Switching Transients at Low Supply Voltage Low Power Mode for Reduced EDGE Current Digital Bias Control for Simple Implementation of Low Power Mode Compact 6mmx6mm Package
TX EN 3 Integrated Power Control VBATT 4
VMODE 5
VRAMP 6
LB RFIN 7 8 VBIAS
12 LB RFOUT
Functional Block Diagram
Product Description
The RF3159 is a high power, dual-mode amplifier module with integrated power control. The input and output terminals are internally matched to 50. The amplifier devices are manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (GaAs HBT) process, which is designed to operate either in saturated mode for GMSK signaling or linear mode for 8PSK signaling. The module is designed to be the final amplification stage in a dual-mode GSM/EDGE mobile transmit lineup operating in the 824MHz to 915MHz (low) and 1710MHz to 1910MHz (high) bands (such as a cellular handset). Band selection is controlled by an input on the module which selects either the low or high band. The device is packaged on a 6mmx6mm laminate module with a protective plastic overmold. Ordering Information
RF3159Quad-Band GSM/EDGE/GSM850/EGSM900 /DCS/PCS/Power Amplifier Module
Applications
Quad-Band GSM/EDGE Handsets GSM/EDGE Transmitter Lineups Portable Battery-Powered Equipment GSM850/EGSM900/DCS/ PCS Products GPRS Class 12 Compatible Products Mobile EDGE/GPRS Data Products
RF3159
RF3159PCBA-41X
Quad-Band GSM/EDGE/GSM850/EGSM900 /DCS/PCS/Power Amplifier Module Power Amplifier Module, 5 Piece Sample Pack Fully Assembled Evaluation Board
Optimum Technology Matching(R) Applied
GaAs HBT GaAs MESFET InGaP HBT SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS Si BJT GaN HEMT
RF MICRO DEVICES(R), RFMD(R), Optimum Technology Matching(R), Enabling Wireless ConnectivityTM, PowerStar(R), POLARISTM TOTAL RADIOTM and UltimateBlueTM are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. (c)2006, RF Micro Devices, Inc.
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RF3159
Absolute Maximum Ratings Parameter
Supply Voltage (VCC) Power Control Voltage (VRAMP) Band Select TX Enable VBIAS VMODE RF - Input Power Max Duty Cycle Output Load VSWR Operating Case Temperature Storage Temperature
Rating
-0.5 to +6.0 -0.5 to +3.0 3.0 3.0 3.0 3.0 12.0 50 10:1 -20 to +85 -55 to +150
Unit
V V V V V V dBm % C C
The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice. RoHS status based on EUDirective2002/95/EC (at time of this document revision).
Caution! ESD sensitive device.
Parameter
VRAMP Power Control
Power Control Range VRAMP Input Current
Min.
0.30
Specification Typ.
Max.
2.2 40
Unit
Condition
V uA VRAMP =VRAMP,MAX
VBIAS
VBIAS "High" VBIAS "Low" VBIAS Input Current -10 1.5 0.7 +10 V V A For low output power levels
VMODE Switch
VMODE "HIGH" VMODE "LOW" VMODE Input Current 1.5 0 -10 1.5 0 -10 1.5 0 -10 3.2 3.0 Off Current 3.6 0.7 +10 4.5 5.5 10 0.7 +10 0.7 +10 V V uA V V uA V V uA V V uA Performance specified Functional with performance degraded TX_EN low PA "ON"
PA "OFF"
8PSK Mode
GMSK Mode
Band Switch
BAND_SEL "HIGH" BAND_SEL "LOW" BAND_SEL Input Current High Band (DCS/PCS)
Low Band (GSM850/GSM900)
TX_EN Switch
TX_EN "HIGH" TX_EN "LOW" TX_EN Input Current
Overall Power Supply
VCC Range
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Parameter
RF Impedance
LB_RF IN LB_RF OUT HB_RF IN HB_RF OUT 50 50 50 50 Nominal Conditions (unless otherwise stated): Input and Output=50, Temp=25 C, VCC =3.6V, VMODE ="Low", Freq=824MHz to 849MHz, 25% Duty Cycle, Pulse Width=1154s, PIN =-2dBm, BAND_SEL="Low", TX_EN="High", VRAMP =VRAMP,MAX 824 -2 34.2 32.0 47 +1 35.0 33.5 53 -84 -80 849 +4 MHz dBm dBm dBm % dBm RBW=100kHz, 869MHz to 894MHz, f0 =849MHz, over PIN range, POUT Min.
Specification Typ.
Max.
Unit
Condition
Cellular 850MHz Band GMSK Mode
Operating Frequency Range Input Power Range, PIN Maximum Output Power 1 Maximum Output Power 2 Total Efficiency (PAE) Output Noise Power
Forward Isolation 1 Forward Isolation 2 2f0 Harmonics 3f0 Harmonics Fundamental Cross Band Coupling 2f0, 3f0 Cross Band Coupling All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability 5:1 -15 -25 -6 -24
-32 -10 -5 -10
dBm dBm dBm dBm dBm dBm
Measured at HB_RFOUT pin, POUT -36 3:1
dBm
Output Load VSWR Ruggedness
10:1
Note: VRAMP,MAX =2.2V, VRAMP,MIN =0.30V, Rated POUT =34.2dBm
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RF3159
Parameter Min. Specification Typ. Max. Unit Condition
Nominal Conditions (unless otherwise stated): Input and Output=50, Temp=25 C, VCC =3.6V, VMODE ="High", VBIAS "High", Freq=824MHz to 849MHz, 25% Duty Cycle, Pulse Width=1154s, BAND_SEL="Low", TX_EN="High" 824 28.5 849 MHz dBm
Cellular 850MHz Band 8PSK Mode
Operating Frequency Range Maximum Output Power Meeting EVM and ACPR Spectrum
13.5 26.0 Gain, High Power Mode Gain, Low Power Mode EVM RMS 31.0 26
20.0 27.0 34.5 31 2.5 37.0 37 5.0 5.0
dBm dBm dB dB % % dBc dBc dBc dBc dBm dBm dBm dBm dBm -36 2.5:1 dBm
VBIAS =Low Temp=-20C to +85C, VCC =3.2V to 4.5V POUT =Rated POUT POUT =13.5dBm, VBIAS =Low POUT ACPR and Spectrum Mask ACPR and Spectrum Mask, Extreme Conditions
-56 -63 -56 -63
Output Noise Power 2f0 Harmonics 3f0 Harmonics Fundamental Cross Band Coupling 2f0, 3f0 Cross Band Coupling All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability Note: Rated POUT =28.5dBm
-82 -15 -25 -6 -24
-80 -7 -10
5:1
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Parameter Min. Specification Typ. Max. Unit Condition
Nominal Conditions (unless otherwise stated): Input and Output=50, Temp=25 C, VCC =3.6V, VMODE ="Low", Freq=880MHz to 915MHz, 25% Duty Cycle, Pulse Width=1154s, PIN =-2dBm, BAND_SEL="Low", TX_EN="High", VRAMP =VRAMP,MAX 880 -2 34.2 32.0 47 +1 34.8 33.5 55 -81 -78 915 +4 MHz dBm dBm dBm % dBm RBW=100kHz, 925MHz to 935MHz, f0 =915MHz, Over PIN range, POUT EGSM 900MHz Band GMSK Mode
Operating Frequency Range Input Power Range, PIN Maximum Output Power 1 Maximum Output Power 2 Total Efficiency (PAE) Output Noise Power
-85
-82
dBm
Forward Isolation 1 Forward Isolation 2 2f0 Harmonics 3f0 Harmonics Fundamental Cross Band Coupling 2f0, 3f0 Cross Band Coupling All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability 5:1 -15 -30 -10 -20
-32 -10 -5 -10
dBm dBm dBm dBm dBm dBm
Measured at HB_RFOUT pin, POUT -36 3:1
dBm
Output Load VSWR Ruggedness
10:1
Note: VRAMP,MAX =2.2V, VRAMP,MIN =0.30V, Rated POUT =34.2dBm
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RF3159
Parameter Min. Specification Typ. Max. Unit Condition
Nominal Conditions (unless otherwise stated): Input and Output=50, Temp=25 C, VCC =3.6V, VMODE ="High", VBIAS ="High", Freq=880MHz to 915MHz, 25% Duty Cycle, Pulse Width=1154s, BAND_SEL="Low", TX_EN="High" 880 28.5 915 MHz dBm
EGSM 900MHz Band 8PSK Mode
Operating Frequency Range Maximum Output Power Meeting EVM and ACPR Spectrum
13.5 26.0 Gain, High Power Mode Gain, Low Power Mode EVM RMS 31.0 26.0
20.0 27.0 33.5 30.5 2.5 36.0 36.0 5.0 5.0
dBm dBm dB dB % % dBc dBc dBc dBc dBm dBm dBm dBm dBm dBm -36 2.5:1 dBm
VBIAS =Low Temp=-20C to +85C, VCC =3.2V POUT =Rated POUT POUT =13.5dBm, VBIAS =Low POUT ACPR and Spectrum Mask ACPR and Spectrum Mask, Extreme Conditions
-56 -63 -56 -63
Output Noise Power
-80 -83
-77 -80 -7 -10
2f0 Harmonics 3f0 Harmonics Fundamental Cross Band Coupling 2f0, 3f0 Cross Band Coupling All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability Note: Rated POUT =28.5dBm
-15 -25 -10 -20
5:1
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Parameter Min. Specification Typ. Max. Unit Condition
Nominal Conditions (unless otherwise stated): Input and Output=50, Temp=25 C, VCC =3.6V, VMODE ="Low", Freq=1710MHz to 1785MHz, 25% Duty Cycle, Pulse Width=1154s, PIN =-2dBm, BAND_SEL="High", TX_EN="High", VRAMP =VRAMP,MAX 1710 -2 32.0 29.5 45 +1 33.5 31.0 49 -81 -77 1785 +4 MHz dBm dBm dBm % dBm RBW=100kHz, 1805MHz to 1880MHz, f0 =1785MHz, over PIN range, POUT DCS 1800MHz Band GMSK Mode
Operating Frequency Range Input Power Range, PIN Maximum Output Power 1 Maximum Output Power 2 Total Efficiency (PAE) Output Noise Power
Forward Isolation 1 Forward Isolation 2 2f0 Harmonics 3f0 Harmonics All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability 5:1 -15 -35
-32 -10 -5 -7 -36 5:1
dBm dBm dBm dBm dBm
Over PIN range, POUT Output Load VSWR Ruggedness
10:1
Note: VRAMP,MAX =2.2V, VRAMP,MIN =0.30V, Rated POUT =32.0dBm
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RF3159
Parameter Min. Specification Typ. Max. Unit Condition
Nominal Conditions (unless otherwise stated): Input and Output=50, Temp=25 C, VCC =3.6V, VMODE ="High", VBIAS "High", Freq=1710MHz to 1785MHz, 25% Duty Cycle, Pulse Width=1154s, BAND_SEL="High", TX_EN="High" 1710 27.5 1785 MHz dBm
DCS 1800MHz Band 8PSK Mode
Operating Frequency Range Maximum Output Power Meeting EVM and ACPR Spectrum
12.5 25.5 Gain, High Power Mode Gain, Low Power Mode EVM RMS 32.0 28.0
18.0 26.5 35.5 34.0 38.0 38.0 5 5
dBm dBm dB dB % % dBc dBc dBc dBc dBm dBm dBm dBm
VBIAS =Low Temp=-20C to +85C, VCC =3.2V POUT =Rated POUT POUT =12.5dBm, VBIAS =Low POUT ACPR and Spectrum Mask ACPR and Spectrum Mask, Extreme Conditions
-56 -63 -56 -63
Output Noise Power 2f0 Harmonics 3f0 Harmonics All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability Note: Rated POUT =27.5dBm
-81 -15 -40
-77 -7 -7 -36 2.5:1
5:1
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Parameter Min. Specification Typ. Max. Unit Condition
Nominal Conditions (unless otherwise stated): Input and Output=50, Temp=25 C, VCC =3.6V, VMODE ="Low", Freq=1850MHz to 1910MHz, 25% Duty Cycle, Pulse Width=1154s, PIN =-2dBm, BAND_SEL="High", TX_EN="High", VRAMP =VRAMP,MAX 1850 -2 32.0 29.5 45 +1 33.5 31.0 52 -82 -77 1910 +4 MHz dBm dBm dBm % dBm RBW=100kHz, 1930MHz to 1990MHz, f0 =1910MHz, over PIN range, POUT PCS 1900MHz Band GMSK Mode
Operating Frequency Range Input Power Range, PIN Maximum Output Power 1 Maximum Output Power 2 Total Efficiency (PAE) Output Noise Power
Forward Isolation 1 Forward Isolation 2 2f0 Harmonics 3f0 Harmonics All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability 5:1 -15 -40
-32 -10 -5 -7 -36 5:1
dBm dBm dBm dBm dBm
Over PIN range, POUT <32dBm Spurious<-36dBm, Set VRAMP where POUT Output Load VSWR Ruggedness
10:1
Note: VRAMP,MAX =2.2V, VRAMP,MIN =0.30V, Rated POUT =32.0dBm
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RF3159
Parameter Min. Specification Typ. Max. Unit Condition
Nominal Conditions (unless otherwise stated): Input and Output=50, Temp=25C, VCC =3.6V, VMODE ="High", VBIAS "High", Freq=1850MHz to 1910MHz, 25% Duty Cycle, Pulse Width=1154s, BAND_SEL="High", TX_EN="High" 1850 27.5 1910 MHz dBm
PCS 1900MHz Band 8PSK Mode
Operating Frequency Range Maximum Output Power Meeting EVM and ACPR Spectrum
12.5 25.5 Gain, High Power Mode Gain, Low Power Mode EVM RMS 32.0 28.0
18.0 26.5 34.5 33.5 37.0 37.0 5 5
dBm dBm dB dB % % dBc dBc dBc dBc dBm dBm dBm dBm
VBIAS =Low Temp=-20C to +85C, VCC =3.2V POUT =Rated POUT POUT =12.5dBm, VBIAS =Low POUT ACPR and Spectrum Mask ACPR and Spectrum Mask, Extreme Conditions
-56 -63 -56 -63
Output Noise Power 2f0 Harmonics 3f0 Harmonics All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability Note: Rated POUT =27.5dBm
-82 -15 -40
-77 -7 -7 -36 2.5:1
5:1
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Pin 1 2 3 4 5 6 Function HB_RFIN BAND_SEL TX_EN VBATT VMODE VRAMP Description
RF input to the high-band PA. It is DC-blocked within the part. Digital input enables either the low band or high band amplifier die within the module. A logic low selects Low Band (GSM850/EGSM900), a low logic high selects High Band (DCS1800/PCS1900). This pin is a high impedance CMOS input with no pull-up or pull-down resistors. Digital input enables or disables the internal circuitry. When disabled, the module is in the OFF state, and draws virtually zero current. This pin is a high impedance CMOS input with no pull-up or pull-down resistors. Main DC power supply for all circuitry in the RF3159. Traces to this pin will have high current pulses during operation so proper decoupling and routing should be observed. Digital input which internally adjusts settings to optimize amplifier performance for saturated or linear mode. A logic low selects saturated mode for GMSK modulation. A logic high selects linear mode for 8PSK modulation. This pin is a high impedance CMOS input with no pull-up or pull-down resistors. In GMSK mode, the voltage on this pin controls the output power by varying the regulated collector voltage of the amplifiers. In EDGE mode, this pin has no effect. An internal 300kHz filter reduces switching ORFS resulting from transitions between DAC steps. Most systems will have no need for external VRAMP filtering. This pin provides an impedance of approximately 60k. RF input to the low-band PA. It is DC-blocked within the part. Bias selection logic pin. A logic low selects a low bias (current saving mode) which will only meet linearity performance at low power levels. A logic high allows linear performance up to the highest supported output power. Ground. Ground. Ground. RF output from the low-band PA. It is DC-blocked within the part. Ground. Ground. Ground. Ground. Ground. RF output from the high-band PA. It is DC-blocked within the part. Ground. Ground. Ground. Ground. Main ground pad in center of part. This pad should be tied to the main ground plane with as little loss as possible for optimum linearity.
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
LB_RFIN VBIAS GND GND GND LB_RFOUT GND GND GND GND GND HB_RFOUT GND GND GND GND GND
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RF3159
Pin Out
GND GND 20 HB RF IN Band Select TX Enable VBATT Mode Select Ramp Signal LB RF IN 1 2 3 4 5 6 7 8 VBIAS 9 GND 10 GND 11 GND 23 GND 22 GND 21 19 GND 18 HB RF OUT
17 GND 16 GND 15 GND
14 GND 13 GND 12 LB RF OUT
Note: view from top of part.
Package Drawing
1.40 1.25
6.00 0.10
6.00 0.10 0.100 TYP 0.975 1.000 TYP 1.725 TYP 5.025 5.400 TYP
0.440 0.050
5.900 TYP 5.325 TYP 5.000 TYP 4.200 TYP 3.325 2.675 2.200 TYP 1.400 TYP 0.675 TYP 0.600 TYP 0.000 0.000 0.600 TYP 0.675 1.400 TYP 2.275 TYP 2.600 TYP 4.200 TYP 4.550 4.950 5.025 5.900 TYP
Shaded area represents pin 1.
Dimensions in mm.
4.575
5.400 TYP 5.325 TYP 5.100 TYP 4.600 TYP 3.800 TYP 3.400 2.600 1.800 TYP 1.000 TYP 0.900 TYP 0.100 TYP
Note: viewed from bottom of the part.
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RF3159
Power On Sequence
GMSK Power On/Off Sequence
3.2 V to 4.5 V VBATT Power On Sequence:
1. Apply VBATT 2. Apply BAND_SEL 3. Apply Low on VMODE 4. Apply RFIN 5. Apply minimum VRAMP (~0.3V) 6. Apply TX_EN 7. Ramp VRAMP for desired output power The Power Down Sequence is the reverse order of the Power On Sequence.
>1.5 V High Band BAND_SEL <0.7 V Low Band
VMODE
<0.7 V GMSK Mode
>1.5 V PA ON TX_EN 2.2V for max POUT VRAMP
~0.3 V for min P
OUT
8PSK Power On/Off Sequence
3.2 V to 4.5 V VBATT >1.5 V High Band BAND_SEL <0.7 V Low Band Power On Sequence:
1. Apply VBATT 2. Apply BAND_SEL 3. Apply High or Low on VBIAS 4. Apply High on VMODE 5. Apply TX_EN 6. Ramp RFIN amplitude for desired output power The Power Down Sequence is the reverse order of the Power On Sequence.
>1.5 V High Power Mode VBIAS <0.7 V Low Power Mode
>1.5 V 8PSK Mode VMODE >1.5 V PA ON TX_EN
~-1 dBm Low Band, ~-5 dBm High Band for rated P
RFIN
OUT
Dual Mode Operation
MODE
GSM 8PSK
VMODE
Low High
VBIAS
Unused FIXED
RF INPUT
VRAMP
Analog voltage that proportionally regulates collector voltage. Controls output power level. (GSM Burst Ramp Control)
TX ENABLE
High (Normal) Low (Isolation)
Ramped burst from Variable Gain Amplifier Unused. High (Normal) High1 or Source (GSM Burst Ramp Control) Low (Isolation) Low2 Note: When VMODE is low (GMSK mode), the voltage on VRAMP is used to regulate the PA collector voltage which directly controls the output power. When VMODE is high (8PSK mode), the PA collector voltage is regulated to 3.6V. The supply for the PA base bias can be selected via the VBIAS pin to optimize current drain for low or high power ranges.
1 2
Normal current consumption for maximum linear output power. Reduced current consumption for improved efficiency at low PCL's.
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RF3159
Application Schematic
HB RFIN 1 18 HB RFOUT
BAND SEL
2
TX EN
3 Integrated Power Control
VBATT+ + Supply Bypass VMODE
4
5
6
VRAMP VMODE
7 8
12
LB RFOUT
VBIAS
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RF3159
Evaluation Board Schematic
50 strip HB RFIN 1 18 50 strip HB RFOUT
BAND SEL TX EN
2
3 Integrated Power Control
VBATT+ + C1 68 F
4
5
VMODE R4 0
0402
6 50 strip 7 12 8 LB RFOUT
VRAMP R5 DNP
0402
LB RFIN
50 strip
J2 Red Banana Receptacle VBATT+
J3 Black Banana Receptacle
VBIAS
1234
J1 4-pin Board-Edge Header Block VBIAS
BAND SEL R1 100 k
0402
VMODE R2 100 k
0402
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RF3159
RF3159 Power Amplifier Simplified Block Diagram of a Single Band
TX_EN VRAMP VBATT
H(s)
RF IN
RF OUT
TX_EN AGC Amplifier
Theory of Operation
Overview The RF3159 is designed for use as the final RF amplifier in GSM850, EGSM900, DCS and PCS handheld digital cellular equipment, and other applications operating in the 824MHz to 915MHz, and 1710MHz to 1910MHz bands. The RF3159 is a high power, dual mode GSM/EDGE, power amplifier with PowerStar(R) integrated power control. The integrated power control circuitry provides reliable control of saturated power by a single analog voltage (VRAMP). This control voltage can be driven directly from a DAC output. PowerStar(R)'s predictable power versus VRAMP relationship allows single-point calibration in each band. Single-point calibration enables handset manufacturers to achieve simple and efficient phone calibration in production. The RF3159 also features an integrated saturation detection circuit, which is an industry first for standard PA module products. The saturation detection circuit automatically monitors battery voltage, and adjusts the power control loop to reduce transient spectrum degradation that would otherwise occur at low battery voltage conditions. Prior to the implementation of the saturation detection circuit, handset designers were required to adjust the ramp voltage within the system software. RFMD's saturation detection circuit reduces handset design time and ensures robust performance over broad operating conditions. The design of a dual mode power amplifier module is a challenging process involving many performance trade-offs and compromises to allow it to perform well in both saturated and linear operating regions. This is most noticeable in the RF3159 GSM efficiency. A GSM only part can have its load line (output match) adjusted for maximum efficiency. In a dual-mode module, tuning of the load line must be balanced between GSM efficiency and EDGE linearity. The result is slightly lower GSM efficiency than a single mode (saturated only) power amplifier module. In addition, the RF3159 uses a special GaAs Heterojunction Bipolar Transistor (HBT) process technology which is not used in the most efficient GSM only power amplifiers. The special HBT process allows the RF3159 to provide excellent linear performance, Error Vector Magnitude (EVM), and Adjacent Channel Power Ratio (ACPR), yet maintain competitive GSM efficiency.
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RF3159
Modes of Operation The RF3159 is a dual-mode saturated GSM and linear EDGE Power Amplifier. In GSM mode, the RF3159 is a traditional PowerStar(R) module, which means that the output power is controlled by the VRAMP voltage. In EDGE mode, the RF3159 acts as a gain block where the output power is controlled by the input RF power. The input RF drive level is reduced from GSM mode to prevent saturation and limit output power. Figure 1 shows the Power Amplifier operating regions in GSM and EDGE mode.
P1 dB 35 dBm
29 dBm
Output Power
GSM GMSK
EDGE 8-PSK
Linear Operation
Saturated Operation
Input Power
Figure 1. RF3159 Power Amplifier Operating Regions in GSM/EDGE Mode GSM applications typically require an input RF drive that is 3dB to 4dB higher than the 1dB compression point. GSM mode involves GMSK modulation, which is a constant envelope modulation and is not sensitive to amplitude non-linearities caused by the PA. Since the useful data in the GMSK modulation is entirely included in the phase, the amplifier may be operated in saturated mode (deep class AB) for optimum efficiency. Saturated output power for the RF3159 is controlled by the voltage on the VRAMP pin. Linear EDGE applications require a linear power amplifier to transfer 8PSK modulation with minimal distortion. Since an 8PSK signal has information encoded in both amplitude and phase, the use of a saturated PA is not trivial and requires a more complex system. The traditional way to design a transmitter that is required to convey both phase and amplitude modulation is through the use of a linear power amplifier (Class A). In the RF3159, the bias is held at a constant level such that the device is operating in linear region, and the output RF level is directly proportional to the input RF level. The RF3159 is used as a linear amplifier by selecting low or high bias mode by a digital signal on the VBIAS pin and reducing the input power to the PA such that the device enters a linear operational region. Output power is controlled by applying the proper amplitude signal to the RF input terminal.
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RF3159
GSM (Saturated) Mode In GSM mode, RF3159 operates as a traditional PowerStar(R) module. The incorporated control loop regulates the collector voltage of the amplifiers while the stages are held at a constant bias. The basic circuit diagram is shown in Figure 2.
VBATT 3 dB BW 300 kHz VRAMP
+
+
Saturation Detector H(s) VCC
RF IN TX ENABLE
RF OUT
Figure 2. RF3159 Basic Circuit Diagram By regulating the collector voltage (VCC), the stages are held in saturation across all power levels. As VCC is decreased, output power decreases as described by Equation 1. The equation shows that load impedance affects output power, but to a lesser degree than VCC supply variations. Since the RF3159 regulates VCC, the dominant cause of power variation is eliminated.
P OUT
dBm
( 2 V CC - V SAT ) = 10 log ------------------------------------------- (Eq. 1) -3 8 R1 10
2
RF3159 power is ramped up and down through the VRAMP control voltage which in turn controls the collector voltage of the amplifier stages. The RF signal applied at the RFIN pin must be a constant amplitude signal and should be high enough to saturate the amplifier in the GSM mode. The input power (PIN) range is indicated in the specifications. Power levels below this range will result in reduced maximum output power and the potential for more variation of output power over extreme conditions. Higher input power is unnecessary and will require more current in the circuitry driving the power amplifier and will increase the minimum output power of the RF3159. The saturation detector circuit monitors the VBATT and VCC voltages and adjusts the power control loop to prevent the seriespass FET regulator from entering saturation. If the VCC regulator were to saturate, the response time would increase dramatically. This is undesirable because the VCC regulator must accurately follow the burst ramp up or ramp down applied to the VRAMP pin, or the transient spectrum will degrade. EDGE (Linear) Mode In EDGE mode, VCC is fixed and one of two preset bias ranges is selectable by the VBIAS pin. EDGE mode gain is reduced from GSM mode by switchable attenuators and the RF3159 operates as a linear amplifier where output power is directly controlled by input power. The RF signal applied to the RFIN pin must be accurately controlled to produce the desired output amplitude and burst ramping. The RFIN power must be maintained so that the amplifier is operating in its linear region. If the input drive is too high, the amplifier will begin to saturate causing the ACPR and EVM performance to degrade. The most sensitive of these on the RF3159 is the +/-400kHz offset ACPR. As the amplifier approaches saturation, this will be the first parameter to show significant degradation. During production calibration of a system containing the RF3159, the PA gain and other parameters must be determined. After that, the RF3159 functions as a fixed gain block while the system adjusts input power such that the output from the transmitter meets the desired system specifications.
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Since the RF3159 operates as a gain block in EDGE mode, gain variation over extreme conditions must be considered when determining the output power that a specific input power will produce. Special attention must be given to ensure that the output power of the PA does not go higher than the maximum linear output that the PA can provide with acceptable EVM and ACPR performance. A large portion of the total current in a linear amplifier is necessary to bias the transistors so that the output remains linear. In an EDGE system where there are a range of output power levels used (PCLs), an amplifier biased to operate at a high power will be very inefficient at low power levels. Conversely, an amplifier biased to operate at a low power will not be linear at high power levels. The maximum linear power of an amplifier is determined during design, but can be adjusted to some extent by the quiescent current through the amplifier transistors. The RF3159 incorporates a digital bias control in EDGE mode. This allows the system designer to select a reduced quiescent current in the power amplifier when operating at lower output power levels, resulting in improved efficiency. Low bias mode for the RF3159 is selected by a low on the VBIAS pin. In low bias mode the PA can only be operated at or below a specified output power level while maintaining linearity. Power Ramping and Timing The RF3159 should be powered on according to the Power-On Sequence provided in the datasheet. The power on sequence is designed to prevent operation of the amplifier under conditions that could cause damage to the device or erratic operation. In the Power-On Sequence, there are some set-up times associated with the control signals of the RF3159. The most important of these is the settling time between TXEN going high and when VRAMP can begin to increase. This time is often referred to as the "pedestal" and is required so that the internal power control loop and bias circuitry can settle after being turned on. The RF3159 requires at least 1.5s or two quarter bit times for proper settling of the power control loop. The diagram below is the ETSI time mask for a single GSM timeslot.
The VRAMP waveform used with the RF3159 must be created such that the output power falls into this power versus time mask. The ability to ramp the RF output power to meet ETSI switching transient and time mask requirements partially depends upon the predictability of output power versus VRAMP response of the power amplifier. The PowerStar(R) control in the RF3159 is very capable of meeting switching transient requirements with the proper raised cosine waveform applied to the VRAMP input. The ramping waveform on VRAMP must not start until after TX_EN is asserted. A ramp of about 12us is required to control switching transients at high power levels.
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The VRAMP voltage range should be limited to min and max values in the specifications to avoid damage or undesirable operation. At some voltage below 0.35V, the CMOS controller switches off and turns off the PA. The effect of this is a discontinuity in the response curve. In order to guarantee minimum switching transients, it is recommended that the minimum ramp voltage be set slightly above the voltage where this discontinuity occurs (See Figure 3). The VRAMP voltage at which the discontinuity occurs is unique to the design of the part and does not shift significantly across process. Figure 3 shows the power versus VRAMP response curve for two parts which represent typical process variation of the discontinuity.
Low Band POUT versus VRAMP
824MHz, 3.6V, PIN=2dBm
35.0
25.0
Output Power (dBm)
15.0
5.0
-5.0
-15.0
-25.0
Sample 1 Sample 2
-35.0 0.0 0.5 1.0 1.5 2.0 2.5
VRAMP (V)
Figure 3. Graph of Output Power versus VRAMP As the VRAMP voltage approaches its maximum, the linear regulator in the CMOS saturates, the output power reaches its maximum level, and the VRAMP versus Output Power curve levels out. The saturation point of the linear regulator is directly proportional to the VBATT supply voltage applied. The VRAMP voltage can be increased above the saturation level, but the PA will not produce any higher output power. It is not recommended to apply a VRAMP voltage above the absolute maximum specification, as the part could be damaged. When the FET pass-device in the linear regulator saturates, the response time of the regulated voltage slows significantly. If the control voltage changes (as in ramp-down) the saturated linear regulator does not react fast enough to follow the ramp-down curve. The result is a discontinuity in the output power ramp and degraded switching transients. This usually occurs at low VBATT levels where the regulated VCC voltage is very near the supply voltage. The RF3159 incorporates a saturation detection circuit which senses if the FET pass-device is entering saturation and reduces VCC to prevent it. This relieves the requirement of the transceiver controller to adjust the maximum VRAMP when the battery voltage is low. Design Considerations There are several key factors to consider in the implementation of a mobile phone transmitter solution using the RF3159: * System efficiency: The RF output match can be designed to improve system efficiency by presenting a non 50 load. Output matching circuits for the RF3159 should be a compromise between system efficiency and power as well as EDGE linearity. Optimal matching for GSM mode alone may degrade the linear performance beyond system specifications.
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* Power variation due to supply voltage: Output power does not vary due to supply voltage under normal operating conditions. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most cases where the PA will be operated. However, as the battery discharges and VBATT approaches its lower operating limit, the output power from the PA will start to drop. This cannot be avoided as a certain supply voltage is required to produce full output power. System specifications must allow for this power decrease. Switching Transients due to low battery conditions are reduced by the saturation detection circuit in RF3159. The saturation detection circuit consists of a feedback loop which detects FET saturation. As the FET approaches saturation, the circuit adjusts the VCC voltage in order to ensure minimum switching transients. The saturation detection circuit is integrated into the CMOS controller and requires no additional input from the user. * Power variation due to temperature RF3159 output power variation due to temperature is largest at low power levels and decreases at the upper power levels. This follows the ETSI specification limits which allow a larger tolerance over extreme conditions at low power levels. Since output power is controlled by an analog input, factors other than the power amplifier will have an effect on total system power variation. The entire system containing the RF3159 should be tested to determine whether compensation is necessary. At high temperatures and low battery voltages, the PA cannot support as high of an output power. In this condition, increasing VRAMP will not provide more output power, so compensation may not provide the intended result. * Noise Power The bias point of the RF3159 is kept constant and the gain in the first stage is always high. This has the effect of maintaining a consistent noise power which does not increase at reduced output power levels. For that reason, noise power is at its highest when VRAMP is at its maximum. The RF3159 does not create enough noise in the receive band to cause system receive band noise power failures, but it may amplify noise from other sources. Care must be taken to prevent noise from entering the power amplifier. * Loop Stability and Loop Bandwidth variation across power levels The design of a proper power control loop involves trade-offs affecting stability, transient spectrum and burst timing. In nonPowerStar(R) architectures, backing off power causes gain variation which can affect loop bandwidth. In RF3159 the loop bandwidth is determined by VCC regulator bandwidth and does not change over output power. Loop stability is maintained since amplifier bias voltage is constant. * Transient Spectrum Switching transients occur when the up and down power ramps are not smooth enough, or suddenly change shape. If the control slope of a PA has an inflection point within the output power control range, or if the slope is too steep, switching transients will result. In RF3159 all stages are kept constantly biased and the output power is controlled by changing the collector voltage according to Equation 1. Inflection points are eliminated by this design. In addition, the steepness of the power control slope is reduced because VRAMP actively controls output power over a larger voltage range than many other power amplifiers. * Harmonics Harmonics are natural products of high efficiency, saturated power amplifiers. An ideal, class 'E', saturated power amplifier will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content. Although this is common to all saturated power amplifiers, there are other factors that contribute to harmonic content as well. With many power control methods, a peak power detector is used to rectify and sense forward power. Through the rectification process, there is additional squaring of the waveform resulting in higher harmonics. The RF3159 has no need for the detector diode; therefore, the harmonics coming out of the PA should represent maximum power of the harmonics throughout the transmit chain. This is based on proper harmonic termination of the transmit port. The receive port termination on antenna switch as well as the harmonic impedance from the switch itself will have an impact on harmonics. These terminations should be adjusted to correct problems with harmonics.
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* Multimode Operation When a GSM TDMA frame contains bursts of different modulation types (EDGE, GSM), a linear EDGE power amplifier must be ramped down, the mode changed, and the power ramped back up again during the guard period between bursts. This requires precise timing of control signals with less room for margin when compared to multiple timeslots with the same modulation. The RF3159 is designed to operate in different modes in adjacent timeslots provided that the control signals are properly applied. The system must be capable of controlling the RF input drive timing separately from the VMODE and VRAMP control signals. Failure to provide the proper timing will produce switching transients.
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RF3159
Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.046", Board Material Rogers RO4003, Multi-Layer
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RF3159
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns for RFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern shown has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. PCB Metal Land and Solder Mask Pattern
A = 0.50 Sq. Typ. B = 0.50 x 0.40 Typ. C = 0.50 x 0.80 0.40 Typ. 5.55 Typ.
Dimensions in mm.
A = 0.64 Sq. Typ. B = 0.64 x 0.54 Typ. C = 0.64 x 0.94 D = 0.45 x 0.57 0.62 Typ.
E = 0.54 x 0.64 F = 0.55 x 0.57 Typ. G = 0.40 x 0.57 Typ. H = 0.50 x 0.40 Typ. I = 0.57 x 0.65 4.67 Typ.
0.85
5.30 Typ. 4.45 3.65 2.65 1.65 0.85 0.00 Typ.
A B B C B B
A
5.55 Typ. 4.90
5.26 5.30 Typ. 4.45 Typ. 3.65 Typ. 2.65 Typ. 1.65 Typ. 0.85 Typ.
5.26
A B B C B B A
D
F
G
A H H I H H
5.55 Typ. 5.26 Typ. 4.75 Typ.
0.40 A B A 0.00 Typ. 0.25 Typ. 0.00 Typ. 0.90 Typ. 1.45 Typ. 3.05 Typ. 3.65 Typ. 4.45 Typ. 5.30 Typ. E F G A
0.55 Typ. 0.04 Typ. -0.25 Typ.
0.00
0.90
1.25
4.90 Typ.
5.30 Typ.
Metal Land Pattern
Solder Mask Pattern
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RoHS* Banned Material Content
RoHS Compliant: Package total weight in grams (g): Compliance Date Code: Bill of Materials Revision: Pb Free Category: Yes 0.122 N/A e4 Pa r ts Pe r Mi l l i o n (PPM ) Pb 0 584 0 0 0 0 0 Cd 0 0 0 0 0 0 0 Hg 0 0 0 0 0 0 0 Cr VI 0 0 0 0 0 0 0 PB B 0 0 0 0 0 0 0 PB DE 0 0 0 0 0 0 0
B i l l o f Ma te r i a l s Sub str a te Pa ssi ve Co mp o ne nts Di e Mo l di ng Co mp o und Di e Atta ch Ep o x y Wi r e So l de r Pl a ti ng
Thi s R o HS b a nne d ma te r i a l co nte nt de cl a r a ti o n wa s pr e p a r e d so l e l y o n i nfo r ma ti o n, i ncl udi ng a na l y ti ca l da ta , pr o vi de d to R F M D by i ts sup pl i e r s, a nd a p p l i e s to the B i l l o f Ma te r i a l s (B OM ) r e vi si o n no te d * DIRECTIVE 2002/95/EC OF THE EUROPEAN PARLIAMENT AND OF THE COUNCIL of 27 January 2003 on the restriction of the use of certain hazardous substances in electrical and electronic equipment Pb noted in this material declaration is used in glass or ceramics in electronic components which is an allowed exemption from the RoHS regulations, see Annex to Directive 2002/95/EC and amendment 2005/747/EC.
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